This invention relates to circuitry which compensates for certain inversions of the information stored within a memory cell, where the inversions occur after the information is written into the cell and before the information is read-out of the cells.
Inversion of the data being stored in the storage cells of a memory array may occur for many different reasons. For example, in dynamic memory systems the data stored in the cells has to be periodically refreshed. To reduce the number of components in the refreshing circuitry a simple inverter, instead of a non-inverting amplifier, may be used. As a result each time the contents of the array are refreshed they are also inverted, (i.e. a "0" is rewritten as a "1" and vice-versa a "1" as a "0".)
Another example of an instance where the contents of a memory cell may be inverted is set forth in my copending application titled, "RANDOM ACCESS MEMORY WITH VOLATILE AND NON-VOLATILE STORAGE" bearing Ser. No. 144,922 and assigned to the same assignee as this application, and the subject matter of which is incorporated herein by reference.
The referenced application discloses a memory cell (see for example cell 10 in FIG. 2 of this application) having a volatile storage section (e.g. 11) and a non-volatile storage section (e.g. 12). Information of first binary significance stored in the volatile section may be transferred to the non-volatile section. Subsequently, the information stored in the non-volatile section may be recalled and transferred back into the volatile section. However, the information transferred back to the volatile section causes the latter to store information of second binary significance. The contents of the volatile section therefore undergo an inversion.